Memory Device

ABSTRACT

A memory device includes a memory cell array including a plurality of memory cells, a common source line to which sources of the plurality of memory cells are commonly connected, and a second electrical connection path further connecting the common source line to a ground voltage using erase-mode memory cells when the common source line forms a first electrical connection path and is connected to the ground voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese patent application No. 2012-169549, filed on Jul. 31, 2012, thedisclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present invention relates to a memory device and, particularly, to amemory device including a common source line that commonly connectssources of a plurality of memory cells.

Flash memory has been widely used as nonvolatile memory, and a largercapacity and a higher speed are demanded with the advancement ofinformation and communications technology.

FIG. 27A shows a structure of a memory cell constituting a typical flashmemory. Note that the memory cell is the minimum unit to storeinformation of “0” or “1”.

As shown in FIG. 27A, a memory cell 10 is one type of MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor) and includes aninsulated floating gate 13, which is different from a typical MOSFET. Aselection gate (word gate) 11 is formed above the floating gate 13, andthe floating gate 13 and the selection gate 11 are insulated from eachother with an inter-polysilicon dielectric film 12 interposedtherebetween. The inter-polysilicon dielectric film 12 is called“inter-poly dielectric (IPD)” because the selection gate 11 and thefloating gate 13 are generally made of polysilicon. Further, a gatedielectric film 14 is formed between the floating gate 13 and a siliconsubstrate, which is the same as a typical MOSFET. Further, inside thesurface of the silicon substrate, electrodes serving as a source 16 anda drain 15 are formed with a gate placed therebetween, which is the sameas a typical MOSFET.

As shown in FIG. 27B, the memory cell 10 performs storage operation byaccumulating charge in the floating gate 13. Because the floating gate13 is completely insulated from the surroundings, it has a structure(nonvolatile structure) where the accumulated charge does not escapefrom the gate even when the power is off. Thus, the memory cell 10stores one bit of data depending on the presence or absence of charge byelectrons in the floating gate 13.

The memory cell array according to related art where such memory cellsare arranged in an array is disclosed in Japanese Unexamined PatentApplication Publication No. 2000-49316. FIGS. 28A to 28C show the memorycell array according to related art disclosed therein.

As shown in FIGS. 28A to 28C, in a memory cell array 900 according torelated art, a source region 903 and a drain region 904 are formedseparately from each other in the surface area of a silicon substrate901. The source region 903 is formed in a continuous pattern along therow direction and commonly connected between adjacent memory cells(common source line). On a channel region between the source region 903and the drain region 904 of each cell transistor, a floating gate 906 isformed with a tunnel oxide film 905 interposed therebetween.

A control gate 908 is formed above the floating gate 906 with adielectric film 907 interposed therebetween. The control gate 908 liesalong the row direction and forms a word line.

On the above-described stacked gate structure, an interlayer dielectricfilm 909 is formed, and a bit line 910 and a source line 911 are formedon the interlayer dielectric film 909 along the column directionintersecting each word line (control gate) 908. The source line 911 isconnected to the source region 903 via a through hole 913 in a sourcecontact portion 912, and the bit _ine 910 is connected to the drainregion 904 via a through hole 914.

SUMMARY

In the memory cell array according to related art disclosed in JapaneseUnexamined Patent Application Publication No. 2000-49316, the commonsource line is formed by commonly connecting the sources of a pluralityof memory cells, and the common source line is provided with a sourcecontact to thereby make a connection from the common source line up to ametal line layer (source line).

By providing the source contact at intervals of several memory cells, itis possible to reduce the circuit area compared with the case ofproviding the source contact at each memory cell.

On the other hand, the manufacturing process of a memory device isbecoming increasingly finer, and the resistance of a source resistorfrom a source region to a metal line of a memory cell is significantlylarge, which hinders high-speed operation. However, if the resistance ofa source resistor is reduced by increasing the number of source contactsin order to enable high-speed operation, the circuit area increases.

Therefore, the memory device according to related art has a problem thatit is difficult to achieve high-speed operation without significantincrease in circuit area.

A first aspect of the present invention is a memory device including amemory cell array including a plurality of memory cells, a common sourceline to which sources of the plurality of memory cells are commonlyconnected in the memory cell array, and a second electrical connectionpath further connecting the common source line to a ground voltage whenthe common source line forms a first electrical connection path and isconnected to the ground voltage, wherein the second electricalconnection path is formed using a first memory cell included in theplurality of memory cells.

A second aspect of the present invention is a memory device including aplurality of memory cells having a source and a drain formed on asurface of a semiconductor substrate and a gate formed including afloating gate on the semiconductor substrate between the source and thedrain, a memory cell array where the plurality of memory cells arearranged in an array, a common source line formed continuously on thesurface of the semiconductor substrate in the memory cell array so thatsources of the plurality of memory cells are commonly connected thereto,an upper source line formed on an interlayer dielectric film on thesemiconductor substrate and connected to the common source line via athrough hole, and a second electrical connection path that connects thecommon source line and a ground voltage without through the upper sourceline when the common source line and the upper source line form a firstelectrical connection path and are connected to the ground voltage,wherein the second electrical connection path is formed using a firstmemory cell included in the plurality of memory cells.

A third aspect of the present invention is a memory device including aplurality of memory cells arranged in an array along a word linedirection and a bit line direction, a common source line that commonlyconnects sources of the plurality of memory cells arranged along theword line direction, and a ground circuit that connects drains of theplurality of memory cells arranged along the bit line direction to aground according to grounding of the common source line.

In the aspects of the present invention, the common source line and theground voltage are connected further by the second electrical connectionpath formed using memory cells, and therefore the resistance of a sourceresistor can be reduced. It is thereby possible to achieve high-speedoperation and suppress an increase in circuit area.

According to the present invention, it is possible to achieve high-speedoperation without significant increase in circuit area.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, advantages and features will be moreapparent from the following description of certain embodiments taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing a structure of a memory deviceaccording to a precondition technique for the present invention;

FIG. 2 is a circuit diagram showing a structure of the memory deviceaccording to the precondition technique for the present invention;

FIG. 3 is a circuit diagram showing a structure of a memory cell arrayaccording to the precondition technique for the present invention;

FIGS. 4A to 4C are diagrams showing a physical structure of a memorycell according to the precondition technique for the present invention;

FIG. 5 is a diagram illustrating an operation of the memory deviceaccording to the precondition technique for the present invention;

FIGS. 6A and 6B are diagrams an operation of the memory device accordingto the precondition technique for the present invention;

FIG. 7 is a diagram illustrating an operation of the memory deviceaccording to the precondition technique for the present invention;

FIGS. 8A and 8B are diagrams an operation of the memory device accordingto the precondition technique for the present invention;

FIG. 9 is a diagram illustrating an operation of the memory deviceaccording to the precondition technique for the present invention;

FIG. 10 is a diagram illustrating an operation of the memory deviceaccording to the precondition technique for the present invention;

FIG. 11 is a diagram illustrating an operation of the memory deviceaccording to the precondition technique for the present invention;

FIGS. 12A and 12B are diagrams an operation of the memory deviceaccording to the precondition technique for the present invention;

FIG. 13 is a diagram illustrating characteristics of the memory deviceaccording to the precondition technique for the present invention;

FIG. 14 is a diagram illustrating characteristics of the memory deviceaccording to the precondition technique for the present invention;

FIG. 15 is a diagram illustrating an outline of the memory deviceaccording to the precondition technique for the present invention;

FIG. 16 is a diagram illustrating an outline of a memory deviceaccording to the present invention;

FIG. 17 is a circuit diagram showing a structure of a memory deviceaccording to a first embodiment of the present invention;

FIG. 18 is a circuit diagram showing a structure of a memory cell arrayaccording to the first embodiment of the present invention;

FIG. 19 is a diagram illustrating an operation of the memory deviceaccording to the first embodiment of the present invention;

FIG. 20 is a diagram illustrating an operation of the memory deviceaccording to the first embodiment of the present invention;

FIG. 21 is a diagram illustrating an operation of the memory deviceaccording to the first embodiment of the present invention;

FIG. 22 is a circuit diagram showing a structure of a memory deviceaccording to a second embodiment of the present invention;

FIG. 23 is a diagram illustrating an operation of the memory deviceaccording to the second embodiment of the present invention;

FIG. 24 is a diagram illustrating an operation of the memory deviceaccording to the second embodiment of the present invention;

FIG. 25 is a diagram illustrating an operation of the memory deviceaccording to the second embodiment of the present invention;

FIG. 26 is a circuit diagram showing a structure of a bit line selectoraccording to a third embodiment of the present invention;

FIGS. 27A and 27B are diagrams showing a structure of a memory cellaccording to related art; and

FIGS. 28A to 28C are diagrams showing a structure of a memory cell arrayaccording to related art.

DETAILED DESCRIPTION Precondition Technique for the Invention

Prior to describing embodiments of the present invention, a memorydevice according to a precondition technique to which the presentinvention is applied is described hereinafter with reference to thedrawings.

FIG. 1 shows a schematic structure of a memory device according to theprecondition technique, and FIG. 2 shows a circuit structure of thememory device according to the precondition technique of FIG. 1.

As shown in FIGS. 1 and 2, a memory device 100 according to theprecondition technique is a NOR (or DINOR) flash memory circuit andincludes a memory cell array unit 110, a word line driver unit 120, asense amplifier unit 130, a bit line selector unit 140, and a sourceline driver unit 150.

The memory cell array unit 110 includes a plurality of memory cellarrays 111. The plurality of memory cell arrays 111 are arranged in anarray in the word line direction (which is the direction along which theword line lies; also called the x-direction) and the bit line direction(which is the direction along which the bit line lies; also called they-direction). Further, each of the memory cell arrays 111 includes aplurality of memory cells and stores 8-bit×8-bit information, asdescribed later.

Note that the number of bits of the memory cell array and the number ofbit lines and word lines in each memory cell array are not limited toeight, and it may be any number. Further, the number of source lines ineach memory cell array is also not limited to one, and it may be anynumber. Furthermore, the number of memory cell arrays and the number ofinputs and outputs of data may be also set to any number.

The word line driver unit 120 includes a plurality of x-address decoders121 and a plurality of word line drivers 122. The plurality of x-addressdecoders 121 are provided in units of the memory cell array 111 and, inthis example, provided in units of eight bits, which is the same as theword ine of the memory cell array 111.

The x-address decoder 121 is connected to the memory cell array 111 by aplurality of word lines 112 through the plurality of word line drivers122. The x-address decoder 121 decodes an x-address signal input from anexternal control circuit and drives the word line 112 corresponding tothe x-address signal by the word line driver 122. The word line driver122 applies a high voltage of memory cells at the writing of memorycells, applies a negative voltage at the erasing of memory cells, andapplies VDD at the reading of memory cells.

The sense amplifier unit 130 includes a plurality of sense amplifiers131 and a plurality of write bit line drivers 132, and the bit lineselector unit 140 includes a plurality of y-address decoders 141 and aplurality of bit line selectors 142.

The sense amplifiers 131, the write bit line drivers 132, the y-addressdecoders 141 and the bit line selectors 142 are provided in units of thememory cell array 111 and, in this example, provided in units of eightbits, which is the same as the bit line of the memory cell array 111.

The bit line selector 142 is connected to the memory cell array 111 by aplurality of bit lines 113 and switches a connection of the bit lines113 of the memory cell array 111 with the sense amplifier 131 or thewrite bit line driver 132.

The y-address decoder 141 decodes a y-address signal input from anexternal control circuit and controls the bit line selector 142 toconnect the bit line 113 corresponding to the y-address signal with thesense amplifier 131 or the write bit line driver 132.

The sense amplifier 131 is connected to a memory cell at the reading ofmemory cells, and amplifies the voltage of the memory cell and output adata output signal to the outside in order to detect the storage mode ofthe memory cell to be read.

The write bit line driver 132 is connected to a memory cell at thewriting of memory cells, and drives the bit line 113 corresponding tothe y-address signal in accordance with a data input signal in order towrite data to the memory cell. The write bit line driver 132 is aninverter and applies VDD to the memory cell by inverting the data inputsignal.

The source line driver unit 150 includes a plurality of source decoders151 and a plurality of source line drivers 152. The plurality of sourcedecoders 151 and the plurality of source line drivers 152 are providedin units of the memory cell array 111. In this example, they areprovided corresponding to a source line 114 of each memory cell array111.

The source decoder 151 is connected to the memory cell array 111 by onesource line 114 through the source line driver 152. The source decoder151 decodes a source address signal input from an external controlcircuit and drives the source line 114 corresponding to the sourceaddress signal by the source line driver 152. The source line driver 152makes switching to apply a high voltage at the writing of memory cellsand connect a memory cell to GND at the reading or erasing of memorycells.

FIG. 3 shows a circuit structure of the memory cell array 111 accordingto the precondition technique. The memory cell array 111 is placed sothat a plurality of word lines 112 and a plurality of bit lines 113intersect with one another, and a plurality of memory cells 201 arearranged in an array at the intersections between the word lines 112 andthe bit lines 113. Further, the source line 114 is led in the word linedirection from the memory cells 201.

In this example, eight word lines 112 (112-0 to 112-7), eight bit lines113 (113-0 to 113-7), and one source line 114 are provided.

In the plurality of memory cells 201 arranged along the word linedirection, the gates of the respective memory cells 201 are commonlyconnected to one word line 112 in each row.

In the plurality of memory cells 201 arranged along the bit linedirection, the drains of the respective memory cells 201 are commonlyconnected to one bit line 113 in each column. Each of the memory cells201 is connected to the bit line 113 through a bit contact 117.

In the plurality of memory cells 201 arranged along the word linedirection, the sources of the respective memory cells 201 are commonlyconnected to one common source line 115 in each row. Further, the memorycells 201 are connected from the common source line 115 to the sourceline 114 through a source contact 116. In this example, one sourcecontact 116 is formed for every eight memory cells 201.

FIGS. 4A to 4C show a physical structure of the memory cell array 111according to the precondition technique shown in FIG. 3. FIG. 4A is aplan view of the memory cell array 111, FIG. 4B is a cross-sectionalview along line X-X′ of FIG. 4A, and FIG. 4C is a cross-sectional viewalong line Y-Y′ of FIG. 4A. Note that, in FIG. 4A, the bit line to whichthe bit contact is connected and the source line to which the sourcecontact is connected are not shown.

As shown in FIGS. 4A to 4C, an isolation oxide film 210 is formed on thesurface of a silicon substrate 200, and a source region 115 and a drainregion 202 are formed separately from each other in the surface area ofthe silicon substrate 200 that is isolated by the isolation oxide film210. The source region 115 is formed in a continuous pattern along thex-direction and commonly connected between adjacent memory cells to formthe common source line 115.

On a channel region between the source region 115 and the drain region202 of each memory cell, a floating gate 205 is formed with a gate oxidefilm 204 interposed therebetween. A selection gate 112 is formed with aninter-polysilicon dielectric film 206 interposed therebetween above thefloating gate 205. The selection gate 112 lies in the x-direction andforms the word line 112.

On the stacked gate structure, an interlayer dielectric film 211 isformed, and the bit line 113 is formed on the interlayer dielectric film211 along the y-direction. Further, the source line (upper source line)114 is formed on the interlayer dielectric film 211 along they-direction, though not shown.

The bit line 113 is connected to the drain region 202 by the bit contact117 via a through hole penetrating the interlayer dielectric film 211.The bit contact 117 is formed for each memory cell as in FIG. 3.

The source line 114 is also connected to the source region (commonsource line) 115 by the source contact 116 via a through holepenetrating the interlayer dielectric film 211. Because the area ofseveral cells is required to form the source contact 116, the sourcecontact 116 is formed for every eight memory cells as in FIG. 3 in thisexample.

A data write operation in the memory device according to theprecondition technique is described hereinafter with reference to FIGS.5, 6A and 6B.

As shown in FIG. 5, when writing data to the memory cell 201, ay-address signal is first input to the y-address decoder 141. They-address decoder 141 decodes the y-address signal and switches the bitline selector 142 so as to connect the bit line 113 connected to amemory cell 201 a to be written and the write bit line driver 132.

Further, a source address signal is input to the source decoder 151. Thesource decoder 151 decodes the source address signal, and the sourceline driver 152 applies a high voltage to the source line 114 in aregion (memory cell array 111) where the memory cell 201 a to be writtenis located.

As the potential of the bit line 113, GND is applied to the cell where 0data is to be written, and VDD is applied to the cell where 1 data is tobe written (i.e. the cell where data is not written). Thus, the bit line113 is applied a voltage generated by inverting input data by the writebit line driver 132.

At this stage, a voltage is not yet applied to the gate 112 through theword line 112, and therefore no current flows into the memory cell 201a. FIGS. 6A and 6B show the state of the memory cell 201 a at this time.

As shown in FIG. 6A, when writing 0 data to the memory cell 201 a, thedrain 202 is set to GND by the bit line 113, a high voltage is appliedto the source 115 by the source line 114, and the gate 112 is GND atthis time.

Further, as shown in FIG. 6B, when writing 1 data (when not writingdata) to the memory cell 201 a, VDD is supplied to the drain 202 by thebit line 113, a high voltage is applied to the source 115 by the sourceline 114, and the gate 112 is GND at this time.

Then, as shown in FIG. 7, an x-address signal is input to the x-addressdecoder 121. The x-address decoder 121 decodes the x-address signal, andthe word line driver 122 applies a high voltage to the word line 112that is connected to the memory cell 201 a to be written correspondingto the x-address. FIGS. 8A and 8B show the state of the memory cell 201a at this time.

As shown in FIG. 8A, for the memory cell 201 a where 0 data is to bewritten, a high voltage is applied to the gate 112 by the word line 112.Then, current flows from the source 115 to the drain 202 in the memorycell 201 a, and electrons (channel hot electrons) having high energythat are generated in the channel of the memory cell 201 a areaccelerated by the high voltage of the gate 112 and injected into thefloating gate 205, and thereby data is written.

Further, as shown in FIG. 8B, for the memory cell 201 a where 1 data isto be written, a high voltage is applied to the gate 112 by the wordline 112. Because the drain 202 is raised to VDD by the bit line 113 inthe memory cell 201 a, no current flows between the source and thedrain, and data is not written to the memory cell 201 a.

A data erase operation in the memory device according to theprecondition technique is described hereinafter with reference to FIG.9.

As shown in FIG. 9, when erasing data of the memory cell 201, thepotential of the bit line 113 is set to GND, the potential of the sourceline 114 is set to GND, and a negative high voltage is applied to theword line 112 that is connected to a memory cell 201 b to be erased.FIG. 10 shows the state of the memory cell 201 b at this time.

As shown in FIG. 10, in the memory cell 201 b, the drain 202 is set toGND by the bit line 113, the source 115 is set to GND by the source line114, and a negative high voltage is applied to the gate 112 by the wordline 112.

Then, electrons accumulated in the floating gate 205 are discharged tothe silicon substrate 200 by Fowler-Nordheim (FN) tunneling phenomenon.Although all of the memory cells 201 b connected in common to the wordline 112 are erased, this raises no problem because in no case aspecific memory cell is erased in the NOR flash memory. Further, ay-address is not required for erasing.

A data read operation in the memory device according to the preconditiontechnique is described hereinafter with reference to FIG. 11.

As shown in FIG. 11, when reading data, a y-address signal is input tothe y-address decoder 141. The y-address decoder 141 decodes they-address signal and switches the bit line selector 142 so as to connectthe bit line 113 connected to a memory cell 201 c to be read and thesense amplifier 131. Further, an x-address signal is input to thex-address decoder 121. The x-address decoder 121 decodes the x-addresssignal and applies a voltage to the word line 112 that is connected tothe memory cell 201 c to be read. Further, the common source line 115and the source line 114 are grounded to GND by the source line driver152. Then, current flows from the memory cell 201 c to GND via the paththrough the common source line 115 and the source line 114 in accordancewith the storage mode of the memory cell 201 c to be read. FIGS. 12A and12B shows the state of the memory cell 201 c at this time.

As shown in FIGS. 12A and 12B, when reading data of the memory cell 201c, the source 115 is set to GND by the source line 114, VDD is suppliedto the gate 112 by the word line 112, and VDD is applied from the senseamplifier 131 to the drain 202 by the bit line 113.

Then, when the memory cell 201 c to be read is “1” which is a non-writestate, no charge is accumulated in the floating gate 205 as shown inFIG. 12A, and therefore an inversion layer is formed at the interface ofthe silicon substrate 200 due to the electric field of the gate 112, andcurrent flows from the drain 202 to the source 115 and flows into GNDthrough the source line 114. The sense amplifier 131 detects thiscurrent and thereby reads the non-write state (data 1).

Further, when the memory cell 201 c to be read is “0” which is a writestate, the voltage applied to the gate 112 is blocked by electrons inthe floating gate 205 and does not reach the silicon substrate 200, andtherefore no current flows between the drain and the source. The senseamplifier 131 detects the absence of current and thereby reads the writestate (data 0).

As described above, in the structure of the precondition technique, thecommon source line that commonly connects the sources of a plurality ofmemory cells is provided, and a connection is made to the source linefrom the common source line through the source contact.

A problem of the precondition technique is as follows. FIG. 13 shows therelationship between the structure of a plurality of memory cellsincluding the precondition technique and source resistance.

In FIG. 13, the structure of “(a) contact for each cell” is a structurein which the source contact is provided for each memory cell, and aconnection is made from the source of each memory cell to the sourceline.

The structure of “(b) silicide common source line” is a structure inwhich the source of each memory cell is connected by silicide (metal),the common source line is formed using this silicide, and a connectionis made from this silicide common source line in units of a plurality ofmemory cells to the source line through the source contact.

The structure of “(c) self-align source” is a structure in which thecommon source line is formed using silicon, in contrast to the structureof the “silicide common source line”.

The structure of “(d) non-silicide common source line” is a structure inwhich the common source line is formed using non-silicide that does notcontain metal because silicide cannot be formed in the source regionbecause of the fine manufacturing process, in contrast to the structureof the “silicide common source line”.

The structure of “(e) buried source line” is a structure in which thecommon source line is formed using non-silicide in a region of anauxiliary electrode such as an erase gate or a region under a dielectricfilm because of the still finer manufacturing process, in contrast tothe structure of the “non-silicide common source line”

Recently, as the manufacturing process becomes finer, the structure ofmemory cells has made progress from the structure (a) to the structure(e). With the progress from the structure (a) to the structure (e), thecell array area is decreasing.

First, comparing the structure (a) with the structures (b) and (c), thestructures (b) and (c) are the structure having the common source linein which the sources of the respective memory cells are commonlyconnected and the source contact is provided at intervals of a pluralityof memory cells, so that the cell array area is smaller than that of thestructure (a).

However, as shown in FIG. 13, because the common source line has higherline resistance than the source line, the source resistance increaseswith use of the common source line.

Further, comparing the structures (b) and (c) with the structures (d)and (e), the area is still smaller in the structures (d) and (e) than inthe structures (b) and (c) by the finer manufacturing process. However,because the source cannot be formed using silicide in the structures (d)and (e) due to the fine manufacturing process, the source resistancesignificantly increases.

The increase in source resistance largely affects cell current flowinginto memory cells. FIG. 14 shows the relationship between the sourcevoltage and the cell current in memory cells. When the source resistanceincreases, the source voltage rises accordingly. Then, the cell currentbecomes lower with the rise of the source voltage as shown in FIG. 14.

Thus, when the source resistance increases, the source voltage cannot bereduced to the ground voltage at the reading of memory cells, and thecell current decreases due to the back-gate effect. As the cell currentis higher, reading can be done at higher speed, and therefore thedecrease in cell current means a decrease in reading speed.

Although one way to reduce the source resistance is to increase thenumber of source contacts, because a source contact region generallyoccupies the area that is several times the size of a normal cell,increasing the number of source contacts results in significantreduction of the effective cell area with respect to the whole cellarray area.

As described above, although the common source line technique iseffective in order to increase the cell density of the NOR flash memory,the source resistance increases and the cell current decreases with useof the technique that is advantageous for the cell density. Further,although it is effective to increase the number of source contacts inorder to reduce the source resistance, the cell density is reducedaccordingly. Thus, the cell density and the source line resistance arein the trade-off relationship.

In view of the above, according to embodiment of the present invention,a discharge path of the source to the ground is created separately tothereby achieve both increase of the cell density and decrease of thesource line resistance, as described hereinbelow. Particularly, forcells in the erase mode, the principle to perform the same operation asa typical MOSFET, such as turning off when a voltage is not applied tothe gate and turning on when a voltage is applied, is used, so that aplurality of paths for the source current can be formed to avoid asignificant increase in circuit area.

(Features of the Invention)

Prior to describing embodiment of the present invention, the mainfeatures of the invention are described hereinafter in comparison withreference examples.

First, FIG. 15 is a schematic diagram at the reading in a memory deviceaccording to a reference example. In the reference example, the senseamplifier 131 is connected to the memory cell 201 c to be read by thebit line selector 142, and the memory cell 201 c to be read is groundedby the source line driver 152 through the common source line 115, thesource contact 116 and the source line 114. The source line 114 is ametal line and has low resistance, and the common source line 115 is adiffusion layer line and has high resistance.

In the reference example, because the diffusion layer line (commonsource line) with high resistance exists in the path from the source ofa memory cell to the ground, the amount of current is restricted. As theamount of current is larger, the reaction of the sense amplifier 131 isfaster, and therefore the resistance needs to be reduced forhigher-speed read operation. To achieve this, however, it is necessaryto provide a large number of diffusion layer—metal line connection(source contact) regions that require a large area, which causes anincrease in the area of the memory cell array.

On the other hand, FIG. 16 is a schematic diagram at the reading in amemory device according to one embodiment of the invention. In thepresent invention, a memory cell 302 that is always in the erase mode isused as the ground path to GND. Specifically, as in the referenceexample, the sense amplifier 131 is connected to a memory cell 301 c tobe read by the bit line selector 142, and the memory cell 301 c (secondmemory cell) to be read is grounded by the source line driver 152 by afirst electrical connection path through the common source line 115, thesource contact 116 and the source line 114. In one embodiment of thisinvention, the memory cell 301 c is also grounded by a second electricalconnection path through the memory cell 302 (first memory cell)connected in common to the common source line 115.

In this manner, according to one embodiment of the invention, cellcurrent is connected to GND not only through the common source line butalso through the memory cell 302, and it is thereby possible to reducethe source resistance and suppress an increase in the source voltage toenable high-speed operation. Further, because the connection is made toGND using a memory cell in the memory cell array rather than a sourcecontract, it is thereby possible to reduce the frequency of placement ofsource contacts and thereby suppress an increase in circuit size.

First Embodiment of the Invention

A first embodiment of the invention is described hereinafter withreference to the drawings. FIG. 17 shows a structure of a memory deviceaccording to the first embodiment of the invention.

A memory device 1 according to this embodiment is a NOR (DINOR) flashmemory circuit and includes the word line driver unit 120, the senseamplifier unit 130, the bit line selector unit 140 and the source linedriver unit 150, which is the same as shown in FIGS. 1 and 2. On theother hand, the memory device 1 includes the memory cell array unit 110that has a different structure from that of FIGS. 1 and 2, and itfurther includes a bit line grounding switch unit 310.

The memory cell array unit 110 includes a plurality of memory cellarrays 300, and each of the memory cell arrays 300 includes a pluralityof memory cells and stores 8-bit×8-bit information, as described later,and further has erase-mode memory cells (memory cells 302, which aredescribed later) that are always in the erase mode. The erase-modememory cells are placed on a specific bit line 113 (bit line 113-G,which is described later), and the specific bit line 113 is connected tothe bit line grounding switch unit 310. Although the specific bit line113 is extended to the bit line selector 142, it is not electricallyconnected to the bit line selector 142.

The bit line grounding switch unit 310 includes a plurality of bit linegrounding switches 311. The plurality of bit line grounding switches 311are provided for each erase-mode memory cell of the memory cell array300 and connected to the erase-mode memory cell by the bit line 113. Thebit line grounding switch 311 is turned on at the reading of a memorycell and thereby connects the erase-mode memory cell to GND.

FIG. 18 shows a circuit structure of the memory cell array 300 accordingto the first embodiment of the invention.

In the memory cell array 300, memory cells 301, which are NOR flashmemory cells, are arranged in an array as in FIG. 3, and the source line114 is connected to each memory cell 301 through the word line 112, thebit line 113 and the common source line 115. The memory cell array 300includes a plurality of erase-mode memory cells 302 that are always inthe erase mode and connected to the bit line 113-G, differently fromFIG. 3. The erase-mode memory cells 302 are always in the erase mode andconnected to the bit line grounding switch 311. As the erase-mode memorycells 302, memory cells connected to an arbitrary bit line 113 may beused. Further, the erase-mode memory cell 302 has the same structure asthe other memory cells and thus has the same physical structure as shownin FIGS. 4A to 4C.

A data write operation in the memory device 1 according to the firstembodiment of the invention is described hereinafter with reference toFIG. 19.

The write operation of the memory device 1 is the same as shown in FIG.5. Specifically, a y-address signal is input to the y-address decoder141, and the bit line selector 142 connects the bit line 113 connectedto a memory cell 301 a to be written and the write bit line driver 132.Further, a source address signal is input to the source decoder 151, andthe source line driver 152 applies a high voltage to the source line 114in a region where the memory cell 301 a to be written is located.Furthermore, an x-address signal is input to the x-address decoder 121,and the word line driver 122 applies a high voltage to the word line 112that is connected to the memory cell 301 a to be written. Data isthereby written to the memory cell 301 a as shown in FIGS. 8A and 8B.

In this embodiment, the bit line 113-G to which the erase-mode memorycells 302 that are always in the erase mode are connected is notconnected to the bit line selector 142 and the write bit line driver132, and therefore the erase-mode memory cells 302 are not selected bythe bit line selector 142 at any time. Further, during writing, the bitline grounding switch 311 is off, and the erase-mode memory cells 302are separated from GND by the switch.

Therefore, electrons are not injected into the erase-mode memory cells302 on the bit line 113-G and remain in the erase mode during writing.Further, address information is not needed for the bit line groundingswitch 311 and it can have a simple structure.

A data erase operation in the memory device according to the firstembodiment of the invention is described hereinafter with reference toFIG. 20.

The erase operation of the memory device 1 is the same as shown in FIG.9. Specifically, when erasing data of the memory cell 301, the potentialof the bit line 113 is set to GND, the potential of the source line 114is set to GND, and a negative high voltage is applied to the word line112 that is connected to a memory cell 301 b to be erased. The data ofthe memory cell 301 b on the word line 112 is thereby erased as shown inFIG. 10.

At this time, the bit line grounding switch 311 is off. Further, becausethe memory cell 301 b to be erased is decided by the x-address only, theerase-mode memory cell 302 is also erased when the memory cell 301 b iserased. Because the erase-mode memory cell 302 should be always in theerase mode, there is no effect on the operation of the invention evenwhen the erase-mode memory cell 302 is erased at the same time as thememory cell 301 b.

A data read operation in the memory device according to the firstembodiment of the invention is described hereinafter with reference toFIG. 21.

When reading data, a y-address signal is input to the y-address decoder141, and the y-address decoder 141 decodes the y-address signal andswitches the bit line selector 142 so as to connect the bit line 113connected to a memory cell 301 c to be read and the sense amplifier 131.Further, an x-address signal is input to the x-address decoder 121, andthe x-address decoder 121 decodes the x-address signal and applies avoltage to the word line 112 that is connected to the memory cell 301 cto be read. Further, the common source line 115 and the source line 114are grounded to GND by the source line driver 152.

At this time, in this embodiment, the bit line grounding switch 311turns on to connect the erase-mode memory cells 302 to GND. When readingdata, the erase-mode memory cells 302 c that are always in the erasemode become the on-state at the same time when a voltage is applied tothe word line 112. The bit line grounding switch 311 is controlled by anexternal control circuit so as to turn on at least during reading ofmemory cells. For example, the bit line grounding switch 311 is turnedon at the timing when the source line driver 152 connects the sourceline 114 to the ground by the source decoder 151.

Therefore, the current that has flowed from the sense amplifier 131 intothe common source line 115 through the memory cell 301 c to be readflows out to GND not only by the path to the source line driver 152 butalso by the path through the erase-mode memory cells 302 c that arealways in the erase mode. Specifically, the memory cell 301 c isgrounded by two paths: a first electrical connection path from thememory cell 301 c to be read (second memory cell) to GND through thecommon source line 115, the source contact 116, the source line 114 andthe source line driver 152, and a second electrical connection path fromthe memory cell 301 c to be read to GND through the common source line115, the source to the drain of the erase-mode memory cells 302 c (firstmemory cell) in the on-state, the bit line 113-G connected to theerase-mode memory cells 302 c, and the bit line grounding switch 311.

As described above, in this embodiment, memory cells that are always inthe erase mode and not used for storage of data are prepared on the sameword line as a memory cell to be read, and a discharge path to theground is prepared on the bit line where the memory cells always in theerase mode exist. The erase-mode memory cells operate in the same manneras normal transistors and thus turn on when a voltage is applied to theword line, so that a path for discharge through the bit line of theerase-mode memory cells is created besides the common source line.

It is thereby possible to reduce the source resistance of memory cellsat the reading. As shown in FIGS. 13 and 14, by reducing the sourceresistance, the source voltage becomes lower to suppress a decrease inthe cell current, thus enabling high-speed operation.

Further, although the memory cell always in the erase mode cannot beused for storing data, because its area is significantly smaller thanthe source contact, an increase in the memory cell array area can beminimum. While the size of the memory cell always in the erase mode isthe width of one memory cell, the size of several cells or larger isrequired for the source contact region. Thus, by reducing the frequencyof placement of source contacts, the proportion of effective cellsincreases, so that an increase in circuit area can be suppressed.

Further, although the source contact portion causes a loss of regularityof the memory cell array and tends to degrade the manufacturing yield,because a grounding path is created by making normal memory cells alwaysin the erase mode in the embodiment of this invention, they can bemanufactured in the same manner as normal memory cells. Accordingly,this does not cause a loss of regularity of the memory cell array, andit is thus possible to improve the stability of lithography and etching,reduce variation of the shape and characteristics of memory cells, andenhance the yield.

For example, when the diffusion layer line resistance is about 500Ω permemory cell width, it has been necessary to provide the cell contactregion for every 16 memory cells in order to achieve high-speed readingof 80 MHz or more in the precondition technique. On the other hand, inthis embodiment, it is only necessary to provide the cell contact regionfor every 128 memory cells by providing the memory cell always in theerase mode for every 16 cells.

For example, when the width of three memory cells is required for thecell contact region, the number of memory cells that can actually storedata increases by about 10% for the same memory cell array area comparedwith the precondition technique.

Second Embodiment of the Invention

A second embodiment of the invention is described hereinafter withreference to the drawings. This embodiment is different from the firstembodiment in that the memory cell always in the erase mode can beplaced on an arbitrary bit line.

FIG. 22 shows a structure of a memory device according to the secondembodiment of the present invention. The memory device 1 according tothis embodiment is different from that of the first embodiment shown inFIG. 17 in the structure of the bit line grounding switch unit 310 andin that it further includes a switch control decoder 312. The otherstructure is the same as that of the first embodiment.

In the bit line grounding switch unit 310, a plurality of bit linegrounding switches 311 are provided corresponding to the respective bitlines 113 of the plurality of memory cell arrays 300. Specifically, thebit line grounding switch 311 selects an arbitrary bit line 113 of thememory cell array 300 and connects it to GND.

The switch control decoder 312 decodes an input switch control signaland switches on and off the bit line grounding switch 311 of thecorresponding bit line 113. Specifically, it separates the bit linewhere a memory cell to be read is placed from GND at the reading of thememory cell.

Further, in this embodiment, because memory cells always in the erasemode can be selected arbitrarily, all bit lines 113 are connected to thebit line selector 142. Note that the structure of the memory cell array300 is the same as that of FIG. 18.

A data write operation in the memory device 1 according to the secondembodiment of the invention is described hereinafter with reference toFIG. 23.

The bit line 113 connected to a memory cell 301 a to be written and thewrite bit line driver 132 are connected according to the y-addresssignal, a high voltage is applied to the source line 114 in a regionwhere the memory cell 301 a to be written is located according to thesource address signal, a high voltage is applied to the word line 112that is connected to the memory cell 301 a to be written according tothe x-address signal, and data is thereby written to the memory cell 301a, in the same manner as shown in FIG. 19.

In this embodiment, the erase-mode memory cells 302 that are always inthe erase mode can be selected arbitrarily, and therefore the y-addressdecoder 141 makes skipping on the bit line 113-G that is connected tothe erase-mode memory cells 302. Thus, the bit line 113-G is notselected according to the y-address, and the erase-mode memory cells 302are not connected to the write bit line driver 132 during writing.Further, because the switch control decoder 312 does not perform controloperation during writing, the bit line grounding switches 311 are alloff, and the erase-mode memory cells 302 are separated from GND by theswitches.

Therefore, electrons are not injected into the erase-mode memory cells302 on the bit line 113-G and remain in the erase mode during writing,just like in FIG. 19. Further, address information is not needed for thebit line grounding switch 311 as in the first embodiment.

Note that, it is feasible that the y-address decoder does not performskipping so that the erase-mode memory cells 302 operate as normalmemory cells 301 to allow writing of given data.

A data erase operation in the memory device according to the secondembodiment of the invention is described hereinafter with reference toFIG. 24.

Just like in FIG. 20, the potential of the bit line 113 is set to GND,the potential of the source line 114 is set to GND, and a negative highvoltage is applied to the word line 112 that is connected to a memorycell 301 b to be erased, so that data of the memory cell 301 b on theword line 112 is erased.

At this time, the switch control decoder 312 does not perform controloperation, and therefore the bit line grounding switches 311 are alloff.

Because the memory cell 301 b to be erased is decided by the x-addressonly, the erase-mode memory cell 302 that should be always in the erasemode is also erased when the memory cell 301 b is erased, as in thefirst embodiment

A data read operation in the memory device according to the secondembodiment of the invention is described hereinafter with reference toFIG. 25.

In the same manner as shown in FIG. 21, the bit line 113 connected to amemory cell 301 c to be read and the sense amplifier 131 are connectedaccording to the y-address signal, a voltage is applied to the word line112 connected to the memory cell 301 c to be read according to thex-address signal, and the common source line 115 and the source line 114are connected to GND.

At this time, in this embodiment, differently from the first embodiment,because there is a path to GND through the bit line grounding switch 311in all bit lines 113, while the bit line where the erase-mode memorycells 302 always in the erase mode are located is connected to GND, thepath to GND needs to be blocked for the bit lines other than theerase-mode memory cells 302.

Therefore, the switch control decoder 312 inputs a switch control signalin accordance with the placement of memory cells and decodes the signalto thereby make control to turn on the bit line grounding switch 311 ofthe bit line 113-G to which the erase-mode memory cells 302 areconnected and turn off the bit line grounding switch 311 of the otherbit lines 113. Note that, although only one bit line 113 is connected toGND in this example, memory cells corresponding to a plurality of bitlines 113 may serve as erase-mode memory cells, and the plurality of bitlines 113 may be grounded.

Then, the current that has flowed from the sense amplifier 131 into thecommon source line 115 through the memory cell 301 c to be read flowsout to GND not only through the source line driver 152 but also throughthe erase-mode memory cells 302 that are always in the erase mode, justlike in the first embodiment.

Therefore, in this embodiment, as in the first embodiment, by the pathfrom the erase-mode memory cells 302 to GND, it is possible to reducethe source resistance to enable high-speed operation and reduce thefrequency of source contacts to suppress an increase in circuit size.

Further, in this embodiment, the discharge path to GND is prepared onall bit lines. It is thereby possible to increase and decrease thenumber of memory cells always in the erase mode according to therequired reading speed.

For example, in the case of a product that requires a large storagecapacity even with low-speed operation, the number of erase-mode memorycells may be controlled to decrease, and in the case of a product thatrequires high-speed operation even with a small storage capacity, thenumber of erase-mode memory cells may be controlled to increase. Theswitching between low-speed reading and high-speed reading can be madesimply by switching the operation of a decoder using an external controlsignal, a fuse or the like, and it is thus possible to produce both of aproduct capable of high-speed reading with a small capacity and aproduct having a large capacity with low-speed operation using the samephotomask.

In the precondition technique, it is necessary to place memory cellsalways in the erase mode for every 16 cells for high-speed reading;however, because there is no need to place memory cells always in theerase mode for low-speed reading of about 10 MHz, for example, thenumber of memory cells further increases by about 6% compared to thefirst embodiment.

Note that, the bit line selector performs skipping to select the memorycells always in the erase mode, and it can be implemented by a controlprogram of a control circuit that supplies a y-address to the memorydevice, for example. This can be introduced at the time of binarygeneration by a compiler or the like of the control program.

In this case, in the circuit structure where the bit line to be skippedis connected to GND, for a CPU where NOP is assigned to data (DD) oferase cells, a part to be set to the erase mode may be kept to FF duringcompilation, and, for a CPU where another instruction is assigned todata (DD) of erase cells, this address may be skipped duringcompilation, for example.

Third Embodiment of the Invention

A third embodiment of the invention is described hereinafter withreference to the drawings. This embodiment is different from the secondembodiment in that the bit line grounding switch is included in the bitline selector.

In the memory device according to this embodiment, the structure of thebit line selector 142 is different from that of FIG. 22 according to thesecond embodiment, and the bit line grounding switches 311 are notneeded. The other structure is the same as that of the secondembodiment.

FIG. 26 shows a structure of a bit line selector according to the thirdembodiment of the invention. The bit line selector 142 includes switches401 for the respective bit lines 113. The switch 401 switches aconnection with the sense amplifier 131 or GND.

As shown in FIG. 25, the path to GND needs to be blocked for the bitlines other than the erase-mode memory cells 302 in the secondembodiment. Although this blocking is switched by the bit line groundingswitches 311 in the second embodiment, it is switched by the switches401 in the bit line selector 142 in this embodiment. Specifically, theswitch 401 connects the bit line 113 connected to the memory cell 301 cto be read to the sense amplifier 131 and connects the other bit lines113 to GND according to the y-address decoder 141.

It is thereby possible to block the path to GND for the bit lines otherthan the erase-mode memory cells in the simpler structure than thesecond embodiment and further suppress an increase in circuit size.

OTHER EMBODIMENTS OF THE INVENTION

It should be noted that the present invention is not restricted to theabove-described embodiments, and various changes and modifications maybe made without departing from the scope of the invention.

For example, the VDD voltage and the GND voltage described in the aboveembodiments are not necessarily the same value, and they may be anyindependent voltages according to need.

For example, the present invention is also applicable to the structurein which a plurality of write states are prepared by adjusting theamount of electrons injected into the floating gate during writing andthe word line voltage during reading, so that data of a plurality ofbits can be stored into one cell.

The first, second and third embodiments can be combined as desirable byone of ordinary skill in the art.

While the invention has been described in terms of several embodiments,those skilled in the art will recognize that the invention can bepracticed with various modifications within the spirit and scope of theappended claims and the invention is not limited to the examplesdescribed above.

Further, the scope of the claims is not limited by the embodimentsdescribed above.

Furthermore, it is noted that, Applicant's intent is to encompassequivalents of all claim elements, even if amended later duringprosecution.

1-18. (canceled)
 19. A memory device, comprising: a sense amplifier; adata memory cell in which data are stored and erased; an erase modememory cell in which data are only erased; a common source line,connected to the data memory cell and the erase mode memory cell, toprovide a first electrical connection path from the data memory cell toa ground voltage; a word line connected to the data memory cell and theerase mode memory cell; a first bit line that connects the senseamplifier to the data memory cell; and a second bit line that connectsthe erase mode memory cell to the ground voltage, wherein, when avoltage is applied to the word line, the erase mode memory cell changesto an on-state to provide a second electrical connection path from thedata memory cell to the ground voltage.
 20. The memory device accordingto claim 19, further comprising a bit line grounding switch thatconnects the second bit line to the ground voltage when data are readfrom the data memory cell.
 21. The memory device according to claim 20,wherein the bit line grounding switch disconnects the second bit linefrom the ground voltage when data are written to the data memory cell.22. The memory device according to claim 20, wherein the bit linegrounding switch disconnects the second bit line from the ground voltagewhen data are erased from the data memory cell.
 23. The memory deviceaccording to claim 19, further comprising a bit line selector thatconnects the first bit line to the sense amplifier.
 24. The memorydevice according to claim 23, further comprising a y-address decoderthat decodes a y-address signal and controls the bit line selector basedon the decoded y-address signal.
 25. The memory device according toclaim 19, further comprising an x-address decoder that decodes anx-address signal and applies the voltage to the word line based on thedecoded x-address signal.
 26. The memory device according to claim 19,further comprising a source line driver that connects the common sourceline to the ground voltage via a source line.
 27. The memory deviceaccording to claim 26, wherein the common source line is a diffusionlayer line having a resistance, and the source line is a metal linehaving a resistance lower than the resistance of the common source line.28. A memory device, comprising: a sense amplifier; a bit line selectorconnected to the sense amplifier; a plurality of data memory cells inwhich data are stored and erased; a plurality of erase mode memory cellsin which data are only erased; a common source line, connected to thedata memory cells and the erase mode memory cells, to provide a firstelectrical connection path from the data memory cells to a groundvoltage; a plurality of word lines connected to the data memory cellsand the erase mode memory cells, each word line being connected to oneof the erase mode memory cells; a plurality of bit lines connected tothe bit line selector and the data memory cells; and a ground bit linethat connects the erase mode memory cells to the ground voltage,wherein, when a voltage is applied to one of the word lines, the erasemode memory cell connected to the word line changes to an on-state toprovide a second electrical connection path from the data memory cellsconnected to the word line to the ground voltage, wherein a y-addressdecoder decodes a y-address signal and controls the bit line selectorbased on the decoded y-address signal, and wherein an x-address decoderdecodes an x-address signal and applies a voltage to one of theplurality of word lines based on the decoded x-address signal.
 29. Thememory device according to claim 28, further comprising a bit linegrounding switch that connects the ground bit line to the ground voltagewhen data are read from one of the plurality of data memory cells. 30.The memory device according to claim 29, wherein the bit line groundingswitch disconnects the ground bit line from the ground voltage when dataare written to one of the plurality of data memory cells.
 31. The memorydevice according to claim 29, wherein the bit line grounding switchdisconnects the ground bit line from the ground voltage when data areerased from one of the plurality of data memory cells.
 32. The memorydevice according to claim 19, further comprising a source line driverthat connects the common source line to the ground voltage via a sourceline.